The present invention relates to integrated circuits (ICs), and more particularly to an interconnect structure, including multilevel interconnect structures, in which dense fringing fields typically present at the bottom corners of the interconnect regions are significantly reduced. The present invention is also directed to a method of fabricating an interconnect structure having reduced fringing fields at the bottom corners of the interconnect regions.
In back end of the line (BEOL) technology, aluminum, Al, and aluminum alloys have been used as the traditional interconnect metallurgies. While aluminum-based metallurgies have been the material of choice for use as metal interconnects over the past years, concern now exists as to whether aluminum will meet the demands as circuit density and speeds for semiconductor devices increase. Because of these growing concerns, other materials have been investigated as possible replacements for aluminum-based metallurgies.
One highly advantageous material now being used as a replacement for aluminum metallurgies is copper, Cu, and Cu alloys. This is because Cu interconnects, i.e., Cu metallic lines, exhibit a lower susceptibility to electromigration failure as compared to Al metal lines. Moreover, copper has a lower resistivity as compared to aluminum which aids in reducing the RC Time constant of a microprocessor.
In addition to the resistivity of the metallic lines, the RC Time Constant is effected by the capacitance of the interlayer dielectric (ILD) in which the metallic lines are formed. Traditionally, silicon dioxide (SiO2; k=4) has been used as the interlayer dielectric material. To lower the capacitance of the interlayer dielectric, and thus lower the RC Time Constant, ILDs having a dielectric constant, k, less than SiO2 are now being used. These so-called low-k ILDs include dielectric materials such as doped silicate glass, polyaromatic ethers, aerogels, xerogels and parylene polymers.
By using ILDs having lower dielectric constants than SiO2 several advantages may be obtained. For example, the use of low-k ILDs has been found to reduce the RC Time Constant due to decreased capacitance. Moreover, the use of low-k ILDs has also been found to improve power dissipation and to reduce crosstalk noise between metallic lines.
The use of a single low-k ILD in interconnect structures causes via etch selectivity problems; therefore, interconnect structures containing a dielectric etch stop layer beneath the low-k ILD are now being typically employed. Specifically, it is known to utilize a dielectric stack that includes a low-k interlayer dielectric layer in which the metallic lines are formed, and an underlying dielectric material for providing etch selectivity to the interconnect structure. The underlying dielectric layer used in such structures to improve via etch selectivity has a higher dielectric constant than the interlayer dielectric and is referred to in the art as well as herein as a xe2x80x98hybridxe2x80x99 dielectric layer.
A typical Cu/low-k BEOL structure is shown in FIG. 1. Specifically, FIG. 1 is a cross-sectional view of a prior art interconnect structure which includes three interconnect levels, labeled as 12a, 12b, and 12c, respectively. Lower interconnect level 12a is formed on a Si-containing substrate 10. Each interconnect level includes a low-k interlayer dielectric 16 formed on a hybrid dielectric layer 14 which has a higher dielectric constant than the low-k interlayer dielectric. Since these two dielectrics have different dielectric constants and are thus composed of different materials, interface 18 exists between the two different dielectrics.
Moreover, Cu lines 20 are shown in each low-k interlayer dielectric and Cu filled via 22 is shown in the uppermost hybrid dielectric layer of interconnect level 12c. A barrier layer 24 is shown separating each successive interconnect level and metallic liner 26 is shown in each metallic line and via.
A major drawback with the prior art interconnect structure of the type shown in FIG. 1 is that dense fringing fields 28 exist at the bottom corners of the metallic lines. Because the bottom corners are coincident i.e., coplanar, with dielectric interface 18, the fringing fields are not completely contained within the boundaries of the low-k dielectric. As such, increased capacitance is observed for this prior art interconnect structure.
In view of the drawbacks mentioned above in respect to prior art interconnect structures, there is a continued need to develop a new and improved low-k interconnect structure in which the capacitance of the interconnect structure is minimized.
One aspect of the present invention relates to a method of fabricating a low-k interconnect structure having reduced fringing fields at the bottom corners of the interconnect structure. Specifically, this aspect of the present invention comprises the steps of:
(a) forming a first interconnect level on a surface of a substrate, said first interconnect level including a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, said first interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric; and
(b) forming a diffusion barrier on said first interconnect level.
In one embodiment of the present invention, the top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric. This embodiment of the present invention is highly preferred since the resultant structure has reduced capacitance as compared to a structure in which the top horizontal portions of the metallic lines are not coplanar with the top surface of the low-k dielectric.
In another embodiment of the present invention, the top horizontal portions of the metallic lines are slightly above the top surface of the low-k dielectric. In such an embodiment, a hard masking cap is present between the metallic lines, and the top portions of the metallic lines are coplanar with the top surface of the hard masking cap.
It is noted that the term xe2x80x9clow-k interlayer dielectricxe2x80x9d refers to any dielectric material that has a relative dielectric constant of less than 4. The term xe2x80x9chybrid dielectricxe2x80x9d is used herein to denote any dielectric material that has a higher dielectric constant than said low-k interlayer dielectric which provides etch selectivity to the interconnect structure. It should be noted that all the dielectric constants specified herein are relative dielectric constants, unless otherwise specified.
Another aspect of the present invention relates to a method of fabricating a multilevel interconnect structure having reduced fringing fields which comprises the steps of:
(a) forming a first interconnect level on a surface of a substrate, said first interconnect level including a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, said first interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric;
(b) forming a diffusion barrier on said first interconnect level; and
(c) forming additional interconnect levels, one on top of each other, wherein each additional interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric.
In the above processing steps used in forming the multilevel interconnect structure, the top horizontal portions of said metallic lines may be coplanar with a top surface of said low-k interlayer dielectric or the top horizontal portions of the metallic lines may be coplanar with a top surface of the hard masking cap.
In yet another aspect of the present invention, an interconnect structure having reduced fringing fields at the bottom corners of said interconnect structure is provided. Specifically, the inventive interconnect structure comprises:
one or more interconnect levels, one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric.
In the above described interconnect structure, the top horizontal portions of said metallic lines may be coplanar with a top surface of said low-k interlayer dielectric or the top horizontal portions of the metallic lines may be coplanar with a top surface of the hard masking cap.